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Pr. Salem Abdennadher
Intel, USA
Pr. Mohamed Masmoudi
National Engineering School of Sfax (ENIS) - Tunisia


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IEEE DTTIS’23 tutorial

Tutorial 1
Design for Excellence Practices for Integrated Circuits

Full name: Dr. Saghir A. Shaikh
Affiliation:Intel Corporation, San Diego, CA.

Presenter Biography:

Saghir A. Shaikh, Ph.D., works as a DFX Technologist at Intel Corporation, San Diego, CA. He has 25 years of design and test implementation experience with companies such as Level One Communications, Sun Microsystems, Cadence Design Systems, and Broadcom Corp. Dr. Shaikh is a Senior Member of the IEEE and Member of IEEE's Test Technology Standards Committee. He has (co)authored more than two dozen papers presented at conferences and published in magazines and journals. He has been on program and paper review committees of several IEEE Conferences. Dr. Shaikh has 20 years of experience presenting and tutoring at IEEE-sponsored events such as International Test Conferences, VLSI Test Symposiums, Asian Test Symposiums, and Latin American Test Workshop.

Tutorial Summary:

The semiconductor supply chain encompasses a web of multiple companies designing, manufacturing, testing, packaging, and distributing semiconductors, often dispersed globally. This mode of the supply chain requires the application of good Design for Excellence (DFX) practices to ensure manufacturability, quality, and profitability. This introductory to intermediate-level tutorial will present an overview of the design stages and tasks for a fabless IC design cycle. It will describe all the key methodologies and techniques used in each task, such as Design for testing, debugging, diagnostics, and manufacturability. What DFX techniques and trade-offs are applicable for each technique, and what return on investment do they bring in cost, quality, yield, and reliability for the high-volume manufactured chips? The DFX techniques for new areas like chips for Artificial Intelligence (AI), data centers, open-source processors, and multi-die packaging and integrated systems will be highlighted in the tutorial.

This tutorial ties all design, test, integration, and manufacturing aspects of IC design. It would benefit the design, test, CAD, and yield engineers and students pursuing careers in these fields, as well as the managers and executives of the semiconductor industry.

Tutorial 2
RISC-V processor for embedded systems

Full name: Pr. Imed Ben Dhaou
Affiliation:Dar Al-Hekma University,SA.

Presenter Biography:

Imed Ben Dhaou: is an associate professor and docent in embedded systems for IoT. Since 2021 he has been with the department of computer science, Dar Al-Hekma University. He has authored and co-authored more than 100 journals and conference papers. Dr. Ben Dhaou received numerous awards including the Best Paper Award from the 1997 Finnish Symposium on Signal Processing, a travel grants from the Ph.D. Forum at DAC, Los Angeles in 2000, publication award from Qassim University, and Dr. Hussein Mohammed Al-Sayyed award for research. Since September 2014, Dr. Ben Dhaou has been serving as an editor to the microelectronics journal, Elsevier. He was the Guest Editor for four special issues in ISI journal. He has served as TPC chair, or TPC member for several conferences in his primary fields of expertise.

Tutorial Summary:

The RISC-V processor is built on an open-source standard that has grown in popularity in recent years due to its ease of use, flexibility, and extensibility. Arm processors, a proprietary instruction set architecture (ISA), have traditionally dominated the embedded system processor market. In recent years, semiconductor and CAD businesses have increased their investment in the development of RISC-V processors, resulting in a CAGR of 146.2%. It is predicted that by 2025, 62.4 billion RISC-V CPU cores will be shipped. The primary goal of this tutorial is to provide attendees with an in-depth understanding of the RISC-V processor architecture, its advantages, and its impact on the field of embedded system. This tutorial is specifically designed for engineers and graduate students who have a basic knowledge of computer architecture and would like to delve deeper into the RISC-V architecture and its applications.